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? semiconductor components industries, llc, 2014 february, 2014 ? rev. 0 1 publication order number: ncp1070/d ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 high-voltage switcher for low power offline smps the ncp107x products integrate a fixed frequency current mode controller with a 700 v mosfet. available in a pdip ? 7 or sot ? 223 package, the ncp107x offer a high level of integration, including soft ? start, frequency ? jittering, short ? circuit protection, skip ? cycle, a maximum peak current set point, ramp compensation, and a dynamic self ? supply (eliminating the need for an auxiliary winding). unlike other monolithic solutions, the ncp107x is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (65, 100 or 130 khz). when the output power demand diminishes, the ic automatically enters frequency foldback mode and provides excellent efficiency at light loads. when the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to a no load condition. protection features include: a timer to detect an overload or a short ? circuit event, overvoltage protection with auto ? recovery and ac input line voltage detection. for improved standby performance, the connection of an auxiliary winding stops the dss operation and helps to reduce input power consumption below 50 mw at high line. features ? built ? in 700 v mosfet with r ds(on) of 4.7 (ncp1076/77) / 11 (ncp1072/75) / 22 (ncp1070/71) ? large creepage distance between high ? voltage pins ? current ? mode fixed frequency operation ? 65 / 100 / 130 khz ? peak current: ncp1070/72 with 250 ma, NCP1071 with 350 ma, ncp1075 with 450 ma, ncp1076 with 650 ma and ncp1077 with 800 ma ? fixed ramp compensation ? skip ? cycle operation at low peak currents only: no acoustic noise! ? dynamic self ? supply: no need for an auxiliary winding ? internal 1 ms soft ? start ? auto ? recovery output short circuit protection with timer ? based detection ? auto ? recovery overvoltage protection with auxiliary winding operation ? frequency jittering for better emi signature, including frequency foldback mode ? no load input consumption < 50 mw ? frequency foldback to improve efficiency at light load ? internal temperature shutdown ? these are pb ? free devices typical applications ? auxiliary / standby isolated power supplies white goods / smart meter / e ? meter sot ? 223 st suffix case 318e marking diagrams http://onsemi.com pdip ? 7 p suffix case 626a 1 x = current limit (0, 1, 2, 5, 6 or 7) y = oscillator frequency = a (65 khz), b (100 khz), c (130 khz) yyy = 065, 100, 130 a = assembly location wl = wafer lot y, yy = year w, ww = work week g or = pb ? free package ayw 107xy p107xpyyy awl yywwg see detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet. ordering information
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 2 pin connections 1 2 3 4 figure 1. pin connections (top view) sot ? 223 v cc 1 2 3 4 8 7 5 v cc (top view) pdip ? 7 gnd fb gnd gnd drain fb drain gnd indicative maximum output power r ds(on) ? i ipk 230 vac 85 ? 265 vac ncp1070 / 1071 22 ? 350 ma 14 w 7.75 w ncp1072 / 1075 11 ? 450 ma 19 w 10 w ncp1076 / 1077 4.7 ? 800 ma 25 w 15 w note: informative values only, with t amb = 50 c, f sw = 65 khz, self supply via auxiliary winding and circuit mounted on minimum copper area as recommended. quick selection table ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 r ds(on) ( ) 22 11 4.7 ipeak (ma) 250 350 250 450 650 800 freq (khz) 65 100 130 * 65 100 130 * 65 100 130 * 65 100 130 65 100 130 * 65 100 130 * note: (*) 130 khz on demand only figure 2. typical application example
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 3 pin function description pin n pin name function pin description 1 v cc powers the internal circuitry this pin is connected to an external capacitor. the v cc includes an active shunt which serves as an auto ? recovery over voltage protection. 2 nc 3 gnd the ic ground 4 fb feedback signal input by connecting an opto ? coupler to this pin, the peak current set point is adjusted accordingly to the output power demand. 5 drain drain connection the internal drain mosfet connection 6 this un ? connected pin ensures adequate creepage distance 7 gnd the ic ground 8 gnd the ic ground vcc vcc management uvlo reset vdd t drain vcc gnd s r q q uvlo + ? osc fb jittering skip i fbskip line detection t recovery scp off skip = ?1? ?? > shut down some blocks to reduce consumption leb + ? soft start reset + ? v clamp + ? 80 ? us filter vcc ovp drv drv dynamic to cs setpoint ipk(0) + ? ipflag ipflag i fbfault i ovp tsd off uvlo lineok lineok reset ss as recovering from scp, tsd, vcc ovp, or uvlo s r q q i fb freeze i sawtooth sawtooth ramp compensation foldback fb(up) r fb(ref) v scp figure 3. simplified internal circuit architecture
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 4 maximum ratings table symbol rating value unit v cc power supply voltage on all pins, except pin 5(drain) ? 0.3 to 10 v bvdss drain voltage ? 0.3 to 700 v i ds(pk) drain current peak during transformer saturation 2 x i ipeak(0) a i_v cc maximum current into pin 1 when activating the 8.2 v active clamp 15 ma r j ? a p suffix, case 626a 0.36 sq. inch 77 c/w junction ? to ? air, 2.0 oz printed circuit copper clad 1.0 sq. inch 60 r j ? a st suffix, plastic package case 318e 0.36 sq. inch 74 c/w junction ? to ? air, 2.0 oz printed circuit copper clad 1.0 sq. inch 55 tj max maximum junction temperature 150 c storage temperature range ? 60 to +150 c esd capability, hbm model (all pins except hv) 2 kv esd capability, machine model 200 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per jedec jesd22 ? a114 ? f machine model method 200 v per jedec jesd22 ? a115 ? a 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, vcc = 8 v unless otherwise noted) symbol rating pin min typ max unit supply section and v cc management v cc(on) v cc increasing level at which the switcher starts operation ncp1070/71/72/75 ncp1076/77 1 1 7.8 7.7 8.2 8.1 8.6 8.5 v v cc(min) v cc decreasing level at which the hv current source restarts 1 6.5 6.8 7.2 v v cc(off) v cc decreasing level at which the switcher stops operation (uvlo) 1 6.1 6.3 6.6 v v cc(reset) v cc voltage at which the internal latch is reset (guaranteed by design) 1 4 v v cc(clamp) offset voltage above v cc(on) at which the internal clamp activates ncp1070/71 ncp1072/75 ncp1076/77 1 1 1 110 130 130 170 190 190 300 300 300 mv i cc1 internal ic consumption, mosfet switching ncp1070/71/72/75 ncp1076/77 1 1 ? ? 0.7 1.0 1.0 1.3 ma i ccskip internal ic consumption, fb is 0 v (no switching on mosfet) 1 360 a 3. the final switch current is: i ipk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built ? in slope compensation, vin the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. ncp1070/71/72/76/77 130 khz on demand only. 5. oscillator frequency is measured with disabled jittering.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, vcc = 8 v unless otherwise noted) symbol unit max typ min pin rating power switch circuit r ds(on) power switch circuit on ? state resistance (id = 50 ma) ncp1070/71 t j = 25 c t j = 125 c ncp1072/75 t j = 25 c t j = 125 c ncp1076/77 t j = 25 c t j = 125 c 5 ? ? ? ? ? ? 22 38 11 19 4.7 8.7 32 55 16 24 6.9 10.75 bv dss power switch circuit & startup breakdown voltage (id (off) = 120 a, t j = 25 c) 5 700 v i dss(off) power switch & startup breakdown voltage off ? state leakage current t j = 125 c (vds = 700 v) 5 85 a t on t off switching characteristics (r l =50 , v ds set for i drain = 0.7 x ilim) turn ? on time (90% ? 10%) turn ? off time (10% ? 90%) 5 5 20 10 ns internal start ? up current source i start1 high ? voltage current source, v = v cc(on) ? 200 mv ncp1070/71/76/77 ncp1072/75 5 5 5.2 5 9.2 9 12.2 12 ma i start2 high ? voltage current source, v cc = 0 v 5 0.5 ma v ccth vcc transient level for istart1 to istart2 toggling point 1 ? 2.2 ? v current comparator i ipk maximum internal current setpoint at 50% duty cycle fb pin open, tj = 25 c ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 ? ? ? ? ? ? 250 350 250 450 650 800 ? ? ? ? ? ? ma i ipk(0) maximum internal current setpoint at beginning of switching cycle fb pin open, tj = 25 c ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 273 382 254 467 689 846 304 425 282 508 765 940 334 467 310 549 841 1034 ma i ipksw final switch current with a primary slope of 200 ma/ s, f sw =65 khz (note 3) ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 ? ? ? ? ? ? 314 427 296 510 732 881 ? ? ? ? ? ? ma 3. the final switch current is: i ipk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built ? in slope compensation, vin the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. ncp1070/71/72/76/77 130 khz on demand only. 5. oscillator frequency is measured with disabled jittering.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, vcc = 8 v unless otherwise noted) symbol unit max typ min pin rating current comparator i ipksw final switch current with a primary slope of 200 ma/ s, f sw =100 khz (note 3) ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 ? ? ? ? ? ? 309 415 293 500 706 845 ? ? ? ? ? ? ma i ipksw final switch current with a primary slope of 200 ma/ s, f sw =130 khz ncp1070 (note 4) NCP1071 (note 4) ncp1072 (note 4) ncp1075 ncp1076 (note 4) ncp1077 (note 4) ? ? ? ? ? ? 303 407 291 493 684 814 ? ? ? ? ? ? ma t ss soft ? start duration (guaranteed by design) ? ? 1 ? ms t prop propagation delay from current detection to drain off state ? ? 100 ? ns internal oscillator f osc oscillation frequency, 65 khz version, tj = 25 c (note 5) ? 59 65 71 khz f osc oscillation frequency, 100 khz version, tj = 25 c (note 5) ? 90 100 110 khz f osc oscillation frequency, 130 khz version, tj = 25 c (note 4 et 5) ? 117 130 143 khz f jitter frequency jittering in percentage of f osc ? ? 6 ? % f swing jittering swing frequency ? ? 300 ? hz d max maximum duty ? cycle ncp1070/71/72/75 ncp1076/77 ? ? 62 65 68 69 72 73 % feedback section i fbfault fb current for which fault is detected 4 ? 35 a i fb100% fb current for which internal current set ? point is 100% (i ipk(0) ) 4 ? 44 a i fbfreeze fb current for which internal current set ? point is i freeze 4 ? ? 90 ? a v fb(ref) equivalent pull ? up voltage in linear regulation range (guaranteed by design) 4 3.3 v r fb(up) equivalent feedback resistor in linear regulation range (guaranteed by design) 4 19.5 k frequency foldback & skip i fbfold start of frequency foldback feedback level 4 ? ? 68 ? a i fbfold(end) end of frequency foldback feedback level, f sw = f min 4 ? ? 100 ? a f min the frequency below which skip ? cycle occurs ? 21 25 29 khz i fbskip the feedback level to enter skip mode 4 ? ? 120 ? a i freeze internal minimum current setpoint (i fb = i fbfreeze ) ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 ? ? ? ? ? ? ? 88 123 88 168 228 280 ? ? ? ? ? ? ma 3. the final switch current is: i ipk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built ? in slope compensation, vin the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. ncp1070/71/72/76/77 130 khz on demand only. 5. oscillator frequency is measured with disabled jittering.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, vcc = 8 v unless otherwise noted) symbol unit max typ min pin rating ramp compensation s a(65) the internal ramp compensation @ 65 khz ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 ? ? ? ? ? ? ? 7 10 4.2 7.5 15 18 ? ? ? ? ? ? ma/ s s a(100) the internal ramp compensation @ 100 khz ncp1070 NCP1071 ncp1072 ncp1075 ncp1076 ncp1077 ? ? ? ? ? ? ? 11 15 6.5 11.5 23 28 ? ? ? ? ? ? ma/ s s a(130) the internal ramp compensation @ 130 khz ncp1070 (note 4) NCP1071 (note 4) ncp1072 (note 4) ncp1075 ncp1076 (note 4) ncp1077 (note 4) ? ? ? ? ? ? ? 14 20 8.4 15 30 36 ? ? ? ? ? ? protections t scp fault validation further to error flag assertion ? 40 53 ? ms t recovery off phase in fault mode ? ? 420 ? ms i ovp v cc clamp current at which the switcher stops pulsing ncp1070/71 ncp1072/75/76/77 1 6.2 6 8.7 8.5 11.2 11 ma t ovp the filter of v cc ovp comparator ? ? 80 ? s v hv(en) the drain pin voltage above which allows mosfet operate, which is detected after tsd, uvlo, scp, or v cc ovp mode. 5 72 91 110 v temperature management tsd temperature shutdown (guaranteed by design) ? 150 c hysteresis in shutdown (guaranteed by design) ? 50 c 3. the final switch current is: i ipk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built ? in slope compensation, vin the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. ncp1070/71/72/76/77 130 khz on demand only. 5. oscillator frequency is measured with disabled jittering. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 8 typical characteristics figure 4. v cc(on) vs. temperature figure 5. v cc(min) vs. temperature figure 6. v cc(off) vs. temperature figure 7. v cc(clamp) vs. temperature figure 8. i cc1 vs. temperature figure 9. r ds(on) vs. temperature 8.4 8.3 8.2 8.1 8.0 7.9 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) v cc(on) (v) 7.0 6.9 6.8 6.7 6.6 6.5 ? 50 ? 25 0 25 50 75 100 125 v cc(min) (v) temperature ( c) 6.6 ? 50 ? 25 0 25 50 75 100 125 v cc(off) (v) temperature ( c) 6.5 6.4 6.3 6.2 6.1 240 220 200 180 160 140 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) v cc(clamp) (v) ? 50 ? 25 0 25 50 75 100 125 temperature ( c) i cc1 (ma) 0.80 0.75 0.70 0.65 0.60 40 20 15 10 5 0 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) r ds(on) ( ) 25 30 35 ncp1070/71 ncp1072/75 ncp1076/77
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 9 typical characteristics figure 10. i dss(off) vs. temperature figure 11. i start1 vs. temperature figure 12. i start2 vs. temperature figure 13. i ipk(0) vs. temperature figure 14. f osc vs. temperature figure 15. d (max) vs. temperature 100 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) i dss(off) ( a) 90 80 70 60 50 ? 50 ? 25 0 25 50 75 100 125 12 11 10 9 8 7 6 5 4 i start1 (ma) ? 50 ? 25 0 25 50 75 100 125 0.6 0.5 0.4 0.3 0.2 0.1 0 temperature ( c) i start2 (ma) temperature ( c) 1000 i ipk(0) (ma) ? 50 ? 25 0 25 50 75 100 125 900 700 600 500 400 300 200 ? 50 ? 25 0 25 50 75 100 125 110 100 90 80 70 60 50 temperature ( c) f osc (khz) ? 50 ? 25 0 25 50 75 100 125 temperature ( c) 72 d max (%) 70 68 66 64 62 110 ncp1075 ncp1072 100 khz 65 khz ncp1076 ncp1077 NCP1071 ncp1070 800
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 10 typical characteristics figure 16. f min vs. temperature figure 17. t scp vs. temperature figure 18. t recovery vs. temperature figure 19. i ovp vs. temperature figure 20. v hv(en) vs. temperature ? 50 ? 25 0 25 50 75 100 125 temperature ( c) 29 f min (khz) 28 27 26 25 24 23 22 21 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) 65 t scp (ms) 60 55 50 45 40 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) 510 t recovery (ms) 490 470 450 430 410 390 370 350 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) 10 i ovp (ma) 9.5 9.0 8.5 8.0 7.5 7.0 ? 50 ? 25 0 25 50 75 100 125 temperature ( c) 110 v hv(en) (v) 105 100 95 90 85 80
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 11 application information introduction the ncp107x offers a complete current ? mode control solution. the component integrates everything needed to build a rugged and low ? cost switch ? mode power supply (smps) featuring low standby power. the quick selection table on page 2 details the differences between references, mainly peak current setpoints and operating frequency. ? current ? mode operation: the controller uses current ? mode control architecture. ? 700 v power mosfet: due to on semiconductor very high voltage integrated circuit technology, the circuit hosts a high voltage power mosfet featuring a 22/11/4.7 r ds(on) ? t j = 25 c. this value lets the designer build a power supply up to respectively 7.75 w, 10 w and 15 w operated on universal mains. an internal current source delivers the startup current, necessary to crank the power supply. ? dynamic self ? supply: due to the internal high voltage current source, this device could be used in the application without the auxiliary winding to provide supply voltage. ? short circuit protection: by permanently monitoring the feedback line activity, the ic is able to detect the presence of a short ? circuit, immediately reducing the output power for a total system protection. a t scp timer is started as soon as the feedback current is below threshold, i fb(fault) , which indicates the maximum peak current. if at the end of this timer the fault is still present, then the device enters a safe, auto ? recovery burst mode, affected by a fixed timer recurrence, t recovery . once the short has disappeared, the controller resumes and goes back to normal operation. ? built ? in v cc over voltage protection: when the auxiliary winding is used to bias the v cc pin (no dss), an internal active clamp connected between v cc and ground limits the supply dynamics to v cc(clamp) . in case the current injected in this clamp exceeds a level of 6.0 ma (minimum), the controller immediately stops switching and waits a full timer period (t recovery ) before attempting to restart. if the fault is gone, the controller resumes operation. if the fault is still there, e.g. a broken opto ? coupler, the controller protects the load through a safe burst mode. ? line detection: an internal comparator monitors the drain voltage as recovering from one of the following situations: ? short circuit protection, ? v cc ovp is confirmed, ? uvlo ? tsd if the drain voltage is lower than the internal threshold (v hv(en) ), the internal power switch is inhibited. this avoids operating at too low ac input. this is also called brown ? in function in some fields. ? frequency jittering: an internal low ? frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering remains active in frequency foldback mode. ? soft ? start: a 1 ms soft ? start ensures a smooth startup sequence, reducing output overshoots. ? frequency foldback capability: a continuous flow of pulses is not compatible with no ? load/light ? load standby power requirements. to excel in this domain, the controller observes the feedback current information and when it reaches a level of i fbfold , the oscillator then starts to reduce its switching frequency as the feedback current continues to increase (the power demand continues to reduce). it can go down to 25 khz (typical) reached for a feedback level of i fbfold(end) (100 a roughly). at this point, if the power continues to drop, the controller enters classical skip ? cycle mode. ? skip: if smps naturally exhibits a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping un ? needed switching cycles, the ncp107x drastically reduces the power wasted during light load conditions.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 12 application information startup sequence when the power supply is first powered from the mains outlet, the internal current source is biased and charges up the v cc capacitor from the drain pin. once the voltage on this v cc capacitor reaches the v cc(on) level, the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power mosfet if the bulk voltage is above v hv(en) level. figure 21 details the simplified internal circuitry. + - v cc(on) v cc(min) i start1 v bulk 5 8 1 c vcc r limit i1 i cc1 i2 v clamp i clamp i clamp > i ovp --> ovp fault drain figure 21. the internal arrangement of the start ? up circuitry being loaded by the circuit consumption, the voltage on the v cc capacitor goes down. when v cc is below v cc(min) level, it activates the internal current source to bring v cc toward v cc(on) level and stops again: a cycle takes place whose low frequency depends on the v cc capacitor and the ic consumption. a 1.4 v ripple takes place on the v cc pin whose average value equals (v cc(on) + v cc(min) )/2. figure 22 portrays a typical operation of the dss.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 13 figure 22. the charge/discharge cycle over a 1 f v cc capacitor as one can see, even if there is auxiliary winding to provide energy for v cc , it happens that the device is still biased by dss during start ? up time or some fault mode when the voltage on auxiliary winding is not ready yet. the v cc capacitor shall be dimensioned to avoid v cc crosses v cc(off) level, which stops operation. the v between v cc(min) and v cc(off) is 0.4 v. there is no current source to charge v cc capacitor when driver is on, i.e. drain voltage is close to zero. hence the v cc capacitor can be calculated using c vcc i cc1 d max f osc v (eq. 1) take the ncp1072 65 khz device as an example. c vcc should be above 0.8m 72% 59 khz 0.4 a margin that covers the temperature drift and the voltage drop due to switching inside fet should be considered, and thus a capacitor above 0.1 f is appropriate. the v cc capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. as one can see on figure 21, an internal active zener diode, protects the switcher against lethal v cc runaways. this situation can occur if the feedback loop optocoupler fails, for instance, and you would like to protect the converter against an over voltage event. in that case, the internal current increase incurred by the v cc rapid growth triggers the over voltage protection (ovp) circuit and immediately stops the output pulses for t recovery duration (420 ms typically). then a new start ? up attempt takes place to check whether the fault has disappeared or not. the ovp paragraph gives more design details on this particular section. fault condition ? short ? circuit on v cc in some fault situations, a short ? circuit can purposely occur between v cc and gnd. in high line conditions (v hv = 370 v dc ) the current delivered by the startup device will seriously increase the junction temperature. for instance, since i start1 equals 5 ma (the min corresponds to the highest t j ), the device would dissipate 370 x 5 m = 1.85 w. to avoid this situation, the controller includes a novel circuitry made of two startup levels, i start1 and i start2 . at power ? up, as long as v cc is below a 2.4 v level, the source delivers i start2 (around 500 a typical), then, when v cc reaches 2.4 v, the source smoothly transitions to i start1 and delivers its nominal value. as a result, in case of short ? circuit between v cc and gnd, the power dissipation will drop to 370 x 500u = 185 mw. figure 22 portrays this particular behavior. the first startup period is calculated by the formula c x v = i x t, which implies a 1 x 2.4 / 500u = 4.8 ms startup time for the first sequence. the second sequence is obtained by toggling the source to 8 ma with a delta v of v cc(on) ? v ccth = 8.2 ? 2.4 = 5.8 v, which finally leads to a second startup time of 1 x 5.8 / 8m = 0.725 ms. the total startup time becomes 4.8m + 0.725m = 5.525 ms. please note that this calculation is approximated by the presence of the knee in the vicinity of the transition.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 14 fault condition ? output short ? circuit as soon as v cc reaches v cc(on) , drive pulses are internally enabled. if everything is correct, the auxiliary winding increases the voltage on the v cc pin as the output voltage rises. during the start ? sequence, the controller smoothly ramps up the peak drain current to maximum setting, i.e. i ipk , which is reached after a typical period of 1 ms. when the output voltage is not regulated, the current coming through fb pin is below i fbfault level (35 a typically), which is not only during the startup period but also anytime an overload occurs, an internal error flag is asserted, ipflag, indicating that the system has reached its maximum current limit set point. the assertion of this flag triggers a fault counter t scp (53 ms typically). if at counter completion, ipflag remains asserted, all driving pulses are stopped and the part stays off in t recovery duration (about 420 ms). a new attempt to re ? start occurs and will last 53 ms providing the fault is still present. if the fault still affects the output, a safe burst mode is entered, affected by a low duty ? cycle operation (11%). when the fault disappears, the power supply quickly resumes operation. figure 23 depicts this particular mode: figure 23. in case of short ? circuit or overload, the ncp107x protects itself and the power supply via a low frequency burst mode. the v cc is maintained by the current source and self ? supplies the controller. auto ? recovery over voltage protection the particular ncp107x arrangement offers a simple way to prevent output voltage runaway when the optocoupler fails. as figure 24 shows, an active zener diode monitors and protects the v cc pin. below its equivalent breakdown voltage, that is to say 8.4 v typical, no current flows in it. if the auxiliary v cc pushes too much current inside the zener, then the controller considers an ovp situation and stops the internal drivers. when an ovp occurs, all switching pulses are permanently disabled. after t recovery delay, it resumes the internal drivers. if the failure symptom still exists, e.g. feedback opto ? coupler fails, the device keeps the auto ? recovery ovp mode. figure 24 shows that the insertion of a resistor ( r limit ) between the auxiliary dc level and the v cc pin is mandatory a) not to damage the internal 8.4 v zener diode during an overshoot for instance (absolute maximum current is 15 ma) b) to implement the fail ? safe optocoupler protection (ovp) as of fered by the active clamp. please note that there cannot be bad interaction between the clamping voltage of the internal zener and v cc(on) since this clamping voltage is actually built on top of v cc(on) with a fixed amount of of fset (200 mv typical). r limit should be carefully selected to avoid triggering the ovp as we discussed, but also to avoid disturbing the v cc in low / light load conditions. the below lines detail how to evaluate the r limit value... self ? supplying controllers in extremely low standby applications often puzzles the designer. actually, if a smps operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 v (v nom ), this voltage can drop below 10 v (v stby ) when entering standby. this is because the recurrence of the switching pulses expands so much that the low frequency re ? fueling rate of the v cc capacitor is not enough to keep a proper auxiliary voltage. figure 25 portrays a typical scope shot of a smps entering deep standby (output un ? loaded). thus, care must be taken when calculating r limit 1) to not trigger the v cc over current latch (by injecting 6 ma into the active clamp ? always use the minimum value for worse case design) in normal operation but 2) not to drop too much voltage over r limit when entering standby. otherwise, the converter will enter dynamic self supply mode (dss mode), which increases the power dissipation. based on these recommendations, we are able to bound r limit between two equations:
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 15 v nom v cc(clamp) i trip r limit v stby v cc(min) i ccskip (eq. 2) where: v nom is the auxiliary voltage at nominal load v stby is the auxiliary voltage when standby is entered i trip is the current corresponding to the nominal operation. it thus must be selected to avoid false tripping in overshoot conditions. always use the minimum of the specification for a robust design, i.e. i trip < i ovp . i ccskip is the controller consumption during skip mode. this number decreases compared to normal operation since the part in standby does almost not switch. it is around 0.36 ma for the ncp1072 65 khz version. v cc(min) is the level above which the auxiliary voltage must be maintained to keep the controller away from the dynamic self supply mode (dss mode), which is not a problem in itself if low standby power does not matter. if a further improvement on standby efficiency is concerned, it is good to obtain v cc around 8 v at no load condition in order not to re ? activate the internal clamp circuit. figure 24. a more detailed view of the ncp 107x offers better insight on how to properly wire an auxiliary winding i clamp > i ovp since r limit shall not bother the controller in standby, e.g. keep v cc to above v cc(min) (7.2 v maximum), we purposely select a v nom well above this value. as explained before, experience shows that a 40% decrease can be seen on auxiliary windings from nominal operation down to standby mode. let?s select a nominal auxiliary winding of 13 v to offer sufficient margin regarding 7.2 v when in standby ( r limit also drops voltage in standby ...). plugging the values in equation 2 gives the limits within which r limit shall be selected: 13 8.4 6m r limit 8 7.2 0.36m that is to say: 0.77 k < rlimit < 2.2 k . if we design a 65 khz power supply delivering 12v, then the ratio between auxiliary and power must be: 13 / 12 = 1.08. the ovp latch will activate when the clamp current exceeds 6 ma. this will occur when vauxiliary grows ? up to: 1. 8.4 + 0.77k x (6m + 0.8m) 13.6 v for the first boundary ( r limit = 0.77 k ) 2. 8.4 + 2.2k x (6m +0.8m) 23.4 v for the second boundary ( r limit = 2.2 k ) due to a 1.08 ratio between the auxiliary v cc and the power winding, the ovp will be seen as a lower overshoot on the real output: 1. 13.6 / 1.08 12.6 v 2. 23.4 / 1.08 21.7 v as one can see, tweaking the r limit value will allow the selection of a given overvoltage output level. theoretically predicting the auxiliary drop from nominal to standby is an
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 16 almost impossible exercise since many parameters are involved, including the converter time constants. fine tuning of r limit thus requires a few iterations and experiments on a breadboard to check the auxiliary voltage variations but also the output voltage excursion in fault. once properly adjusted, the fail ? safe protection will preclude any lethal voltage runaways in case a problem would occur in the feedback loop. figure 25. the burst frequency becomes so low that it is difficult to keep an adequate level on the auxiliary v cc ... figure 26 describes the main signal variations when the part operates in auto ? recovery ovp: figure 26. if the v cc current exceeds a certain threshold, an auto ? recovery protection is activated
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 17 improving the precision in auto ? recovery ovp given the ovp variations the internal trip current dispersion incur, it is sometimes more interesting to explore a different solution, improving the situation to the cost of a minimal amount of surrounding elements. figure 27 shows that adding a simple zener diode on top of the limiting resistor, offers a better precision since what matters now is the internal v cc(on) breakdown plus the zener voltage. a resistor in series with the zener diodes keeps the maximum current in the v cc pin below the maximum rating of 15 ma just before trip the ovp. vcc rlimit d1 laux ground figure 27. a simple zener diode added in parallel soft ? start the ncp107x features a 1 ms soft ? start which reduces the power ? on stress but also contributes to lower the output overshoot. figure 28 shows a typical operating waveform. the ncp107x features a novel patented structure which offers a better soft ? start ramp, almost ignoring the start ? up pedestal inherent to traditional current ? mode supplies: vcc on drain current figure 28. the 1 ms soft ? start sequence jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. the ncp107x offers a 6% deviation of the nominal switching frequency. the sweep sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 hz. figure 29 shows the relationship between the jitter ramp and the frequency deviation. it is not possible to externally disable the jitter.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 18 65khz 68.9khz 61.1khz jitter ramp internal sawtooth adjustable figure 29. modulation effects on the clock signal by the jittering sawtooth line detection an internal comparator monitors the drain voltage as recovering from one of the following situations: ? short circuit protection, ? v cc ovp is confirmed, ? uvlo ? tsd if the drain voltage is lower than the internal threshold v hv(en) (91 vdc typically), the internal power switch is inhibited. this avoids operating at too low ac input. this is also called brown ? in function in some fields. frequency foldback the reduction of no ? load standby power associated with the need for improving the ef ficiency, requires to change the traditional fixed ? frequency type of operation. this device implements a switching frequency folback when the feedback current passes above a certain level, i fbfold , set around 68 a. at this point, the oscillator enters frequency foldback and reduces its switching frequency. the internal peak current set ? point is following the feedback current information until its level reaches the minimal freezing level point of i freeze . the only way to further reduce the transmitted power is to diminish the operating frequency down to f min (25 khz typically). this value is reached at a feedback current level of i fbfold(end) . below this po int, if the output power continues to decrease, the part enters skip cycle for the best noise ? free performance in no ? load conditions. figures 30 and 31 depict the adopted scheme for the part. figure 30. by observing the current on the feedback pin, the controller reduces its switching frequency for an improved performance at light load
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 19 figure 31. ipk set ? point is frozen at lower power demand. feedback and skip figure 32 depicts the relationship between feedback voltage and current. the feedback pin operates linearly as the absolute value of feedback current (i fb ) is above 40 a. in this linear operating range, the dynamic resistance is 19.5 k typically (r fb(up) ) and the effective pull up voltage is 3.3 v typically (v fb(ref) ). when i fb is below 40 a, the fb voltage will jump to close to 4.5 v. figure 32. feedback voltage vs. current figure 33 depicts the skip mode block diagram. when the fb current information reaches i fbskip , the internal clock to set the flip ? flop is blanked and the internal consumption of the controller is decreased. the hysteresis of internal skip comparator is minimized to lower the ripple of the auxiliary voltage for v cc pin and v out of power supply during skip mode. it easies the design of v cc over load range.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 20 figure 33. skip cycle schematic ramp compensation and ipk set ? point in order to allow the ncp107x to operate in ccm with a duty cycle above 50%, a fixed slope compensation is internally applied to the current ? mode control. here we got a table of the ramp compensation, the initial current set point, and the final current set ? point of different versions of switcher. fsw sa ipk(duty = 50%) ipk(0) ncp1070 65 khz 7 ma/ s 250 ma 304 ma 100 khz 11 ma/ s 130 khz 14 ma/ s NCP1071 65 khz 10 ma/ s 350 ma 425 ma 100 khz 15 ma/ s 130 khz 20 ma/ s ncp1072 65 khz 4.2 ma/ s 250 ma 282 ma 100 khz 6.5 ma/ s 130 khz 8.4 ma/ s ncp1075 65 khz 7.5 ma/ s 450 ma 508 ma 100 khz 11.5 ma/ s 130 khz 15 ma/ s ncp1076 65 khz 15 ma/ s 650 ma 732 ma 100 khz 23 ma/ s 130 khz 30 ma/ s ncp1077 65 khz 18 ma/ s 800 ma 904 ma 100 khz 28 ma/ s 130 khz 36 ma/ s
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 21 the figure 34 depicts the variation of i pk set ? point vs. the power switcher duty ratio, which is caused by the internal ramp compensation. figure 34. i pk set ? point varies with power switch on time, which is caused by the ramp compensation design procedure the design of an smps around a monolithic device does not differ from that of a standard circuit using a controller and a mosfet. however, one needs to be aware of certain characteristics specific of monolithic devices. let us follow the steps: v in min = 90 vac or 127 vdc once rectified, assuming a low bulk ripple v in max = 265 vac or 375 vdc v out = 12 v p out = 10 w operating mode is ccm = 0.8 1. the lateral mosfet body ? diode shall never be forward biased, either during start ? up (because of a large leakage inductance) or in normal operation as shown by figure 35. this condition sets the maximum voltage that can be reflected during t off . as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you thus must adopt a turn ratio which adheres to the following equation: n v out v f v in,min (eq. 3) 2. in our case, since we operate from a 127 v dc rail while delivering 12 v, we can select a reflected voltage of 120 vdc maximum. therefore, the turn ratio np:ns must be smaller than v reflect v out v f
120 12 0.5
9.6 or np:ns < 9.6. here we choose n = 8 in this case. we will see later on how it affects the calculation. 1.004m 1.011m 1.018m 1.025m 1.032m ? 50.0 50.0 150 250 350 > 0 !! figure 35. the drain ? source wave shall always be positive
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 22 figure 36. primary inductance current evolution in ccm i lavg 3. lateral mosfets have a poorly doped body ? diode which naturally limits their ability to sustain the avalanche. a traditional rcd clamping network shall thus be installed to protect the mosfet. in some low power applications, a simple capacitor can also be used since v drain,max
v in n v out v f i peak l f c tot (eq. 4) where l f is the leakage inductance, c tot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), n the n p :n s turn ratio, v out the output voltage, v f the secondary diode forward drop and finally, i peak the maximum peak current. w orse case occurs when the smps is very close to regulation, e.g. the v out target is almost reached and i peak is still pushed to the maximum. for this design, we have selected our maximum voltage around 650 v (at v in = 375 vdc). this voltage is given by the rcd clamp installed from the drain to the bulk voltage. we will see how to calculate it later on. 4. calculate the maximum operating duty ? cycle for this flyback converter operated in ccm: d max
n v out v f n v out v f v in,min
1 1 v in,min n v out v f
0.44 (eq. 5) 5. to obtain the primary inductance, we have the choice between two equations: l
v in d 2 f sw kp in (eq. 6) where k
i l i lavg and defines the amount of ripple we want in ccm (see figure 36). ? small k: deep ccm, implying a large primary inductance, a low bandwidth and a large leakage inductance. ? large k: approaching bcm where the rms losses are worse, but smaller inductance, leading to a better leakage inductance. from equation 6, a k factor of 1 (50% ripple), gives an inductance of: l
( 127 0.44 ) 2 65k 1 12.75
3.8 mh
223 ma peak ? to ? peak i l
v in,min d max lf sw
127 0.44 3.8 65k the peak current can be evaluated to be: i peak
i avg d i l 2
i peak
98m 0.44 i l 2
335 ma on i l , i lavg can also be calculated: i lavg
i peak i l 2
0.34 0.112
223 ma 6. based on the above numbers, we can now evaluate the conduction losses: i d,rms
d i peak 2 i peak i l i l 2 3
0.44 0.335 2 0.335 0.223 0.223 2 3
154 ma if we take the maximum r ds(on) for a 125 c junction temperature, i.e. 24 , then conduction losses worse case are: p cond
i d,rms 2 r ds(on)
570 mw 7. off ? time and on ? time switching losses can be estimated based on the following calculations: p off
i peak v bulk v clamp t off 2t sw (eq. 7)
0.335 ( 127 120 2 ) 10n 2 15.4
36 mw
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 23 where, assume the v clamp is equal to two times of reflected voltage. p on
i valley v bulk n v out v f t on 6t sw (eq. 8)
0.111 ( 127 100 ) 20n 6 15.4
5.5 mw it is noted that the overlap of voltage and current seen on mosfet during turning on and off duration is dependent on the snubber and parasitic capacitance seen from drain pin. therefore the t off and t on in equations 7 and 8 have to be modified after measuring on the bench. 8. the theoretical total power is then 0.570 + 0.036 + 0.0055 = 611 mw 9. if the ncp107x operates at dss mode, then the losses caused by dss mode should be counted as losses of this device on the following calculation: p dss
i cc1 v in,max
1m 375
375 mw (eq. 9) mosfet protection as in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the mosfet bvdss which is 700 v. figure 37a, b, c present possible implementations: figure 37. different options to clamp the leakage spike ab c figure 37 a : the simple capacitor limits the voltage according to the lateral mosfet body ? diode shall never be forward biased, either during start ? up (because of a large leakage inductance) or in normal operation as shown by figure 35. this condition sets the maximum voltage that can be reflected during t off . as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you thus must adopt a turn ratio which adheres to the following equation: equation 3. this option is only valid for low power applications, e.g. below 5 w, otherwise chances exist to destroy the mosfet. after evaluating the leakage inductance, you can compute c with equation 4. typical values are between 100 pf and up to 470 pf. large capacitors increase capacitive losses... figure 37 b : the most standard circuitry is called the rcd network. you calculate r clamp and c clamp using the following formulae: r clamp
2v clamp v clamp v out v f n l leak i peak 2 f sw (eq. 10) c clamp
v clamp v ripple f sw r clamp (eq. 11) v clamp is usually selected 50 ? 80 v above the reflected value n x (v out + v f ). the diode needs to be a fast one and a mur160 represents a good choice. one major drawback of the rcd network lies in its dependency upon the peak current. w orse case occurs when i peak and v in are maximum and v out is close to reach the steady ? state value. figure 37 c : this option is probably the most expensive of all three but it offers the best protection degree. if you need a very precise clamping level, you must implement a zener diode or a tvs. there are little technology differences behind a standard zener diode and a tvs. however, the die area is far bigger for a transient suppressor than that of zener. a 5 w zener diode like the 1n5388b will accept 180 w peak power if it lasts less than 8.3 ms. if the peak current in the worse case (e.g. when the pwm circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 w, then the diode will be destroyed when the supply experiences overloads. a transient suppressor like the p6ke200 still dissipates 5 w of continuous power but is able to accept surges up to 600 w @ 1 ms. select the zener or tvs clamping level between 40 to 80 v above the reflected output voltage when the supply is heavily loaded.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 24 power dissipation and heatsinking the ncp107x welcomes two dissipating terms, the dss current ? source (when active) and the mosfet. thus, p tot = p dss + p mosfet . it is mandatory to properly manage the heat generated by losses. if no precaution is taken, risks exist to trigger the internal thermal shutdown (tsd). to help dissipating the heat, the pcb designer must foresee large copper areas around the package. t ake the pdip ? 7 package as an example, when surrounded by a surface greater than 1.0 cm 2 of 35 m copper, it becomes possible to drop its thermal resistance junction ? to ? ambient, r ja down to 75 c/w and thus dissipate more power. the maximum power the device can thus evacuate is: p max
t jmax t ambmax r ja (eq. 12) which gives around 930 mw for an ambient of 50 c and a maximum junction of 120 c. if the surface is not large enough, assuming the r ja is 100 c/w, then the maximum power the device can evacuate becomes 700 mw. figure 38 gives a possible layout to help drop the thermal resistance. figure 38. a possible pcb arrangement to reduce the thermal resistance junction ? to ? ambient a 10 w ncp1075 based flyback converter featuring low standby power figure 40 depicts a typical application showing a ncp1075 ? 65 khz operating in a 10 w converter. to leave more room for the mosfet, it is recommended to disable the dss by shorting the j3. in this application, the feedback is made via a ncp431 whose low bias current (50 a) helps to lower the no load standby power. measurements have been taken from a demonstration board implementing the diagram in figure 40 and the following results were achieved with auxiliary winding to bias the device: 100 vac 115 vac 230 vac 265 vac no load consumption with auxiliary winding 26 mw 28 mw 38 mw 45 mw
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 25 figure 39. v out = 12 v figure 40. a 12 v ? 0.85 a universal mains power supply r_l3 15 t1 ma5597 ? al c9 10 nf
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 26 ordering information device frequency package type shipping rds(on) ohm ipk (ma) ncp1070stat3g 65 khz sot ? 223 4000 / tape & reel 22 250 ncp1070stbt3g 100 khz sot ? 223 4000 / tape & reel 22 250 ncp1070p065g 65 khz pdip ? 7 50 units / rail 22 250 ncp1070p100g 100 khz pdip ? 7 50 units / rail 22 250 NCP1071stat3g 65 khz sot ? 223 4000 / tape & reel 22 350 NCP1071stbt3g 100 khz sot ? 223 4000 / tape & reel 22 350 NCP1071p065g 65 khz pdip ? 7 50 units / rail 22 350 NCP1071p100g 100 khz pdip ? 7 50 units / rail 22 350 ncp1072stat3g 65 khz sot ? 223 4000 / tape & reel 11 250 ncp1072stbt3g 100 khz sot ? 223 4000 / tape & reel 11 250 ncp1072p065g 65 khz pdip ? 7 50 units / rail 11 250 ncp1072p100g 100 khz pdip ? 7 50 units / rail 11 250 ncp1075stat3g 65 khz sot ? 223 4000 / tape & reel 11 450 ncp1075stbt3g 100 khz sot ? 223 4000 / tape & reel 11 450 ncp1075stct3g 130 khz sot ? 223 4000 / tape & reel 11 450 ncp1075p065g 65 khz pdip ? 7 50 units / rail 11 450 ncp1075p100g 100 khz pdip ? 7 50 units / rail 11 450 ncp1075p130g 130 khz pdip ? 7 50 units / rail 11 450 ncp1076stat3g 65 khz sot ? 223 4000 / tape & reel 4.7 650 ncp1076stbt3g 100 khz sot ? 223 4000 / tape & reel 4.7 650 ncp1076p65g 65 khz pdip ? 7 50 units / rail 4.7 650 ncp1076p100g 100 khz pdip ? 7 50 units / rail 4.7 650 ncp1077stat3g 65 khz sot ? 223 4000 / tape & reel 4.7 800 ncp1077stbt3g 100 khz sot ? 223 4000 / tape & reel 4.7 800 ncp1077p65g 65 khz pdip ? 7 50 units / rail 4.7 800 ncp1077p100g 100 khz pdip ? 7 50 units / rail 4.7 800 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 27 package dimensions sot ? 223 (to ? 261) case 318e ? 04 issue n a1 b1 d e b e e1 4 123 0.08 (0003) a l1 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inch. 1.5 0.059 mm inches scale 6:1 3.8 0.15 2.0 0.079 6.3 0.248 2.3 0.091 2.3 0.091 2.0 0.079 h e dim a min nom max min millimeters 1.50 1.63 1.75 0.060 inches a1 0.02 0.06 0.10 0.001 b 0.60 0.75 0.89 0.024 b1 2.90 3.06 3.20 0.115 c 0.24 0.29 0.35 0.009 d 6.30 6.50 6.70 0.249 e 3.30 3.50 3.70 0.130 e 2.20 2.30 2.40 0.087 0.85 0.94 1.05 0.033 0.064 0.068 0.002 0.004 0.030 0.035 0.121 0.126 0.012 0.014 0.256 0.263 0.138 0.145 0.091 0.094 0.037 0.041 nom max l1 1.50 1.75 2.00 0.060 6.70 7.00 7.30 0.264 0.069 0.078 0.276 0.287 h e ? ? e1 0 1 0 0 1 0 l l 0.20 ??? ??? 0.008 ??? ??? *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1070, NCP1071, ncp1072, ncp1075, ncp1076, ncp1077 http://onsemi.com 28 package dimensions pdip ? 7 (pdip ? 8 less pin 6) case 626a issue b 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs ? 3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension e3 is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 m 8x c d1 b h note 5 e e/2 a2 note 3 m b m note 6 m dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1070/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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